? semiconductor components industries, llc, 2001 june, 2001 rev. 7 1 publication order number: sn74ls109a/d sn74ls109a dual jk positive edge-triggered flip-flop the sn74ls109a consists of two high speed completely independent transition clocked jk flip-flops. the clocking operation is independent of rise and fall times of the clock waveform. the jk design allows operation as a d flip-flop by simply connecting the j and k pins together. mode select truth table operating mode inputs outputs operating mode s d c d j k q q set reset (clear) *undetermined load a1o (set) hold toggle load a0o (reset) l h l h h h h h l l h h h h x x x h l h l x x x h h l l h l h h q q l l h h l q q h * both outputs will be high while both s d and c d are low, but the output states are unpredictable if s d and c d go high simultaneously. h, h = high voltage level l, i = low voltage level x = don't care l, h (q) = lower case letters indicate the state of the referenced input i, h (q) = (or output) one set-up time prior to the low to high clock transition. guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky device package shipping ordering information sn74ls109an 16 pin dip 2000 units/box sn74ls109ad soic16 soic d suffix case 751b http://onsemi.com 38 units/rail plastic n suffix case 648 16 1 16 1 sn74ls109adr2 soic16 2500/tape & reel sn74ls109am soeiaj16 see note 1 sn74ls109amel soeiaj16 1. for ordering information on the eiaj version of the soic package, please contact your local on semiconductor representative. see note 1 soeiaj m suffix case 966 16 1 http://onsemi.com
http://onsemi.com 2 logic diagram set (s d ) clear (c d ) 5(11) 1(15) clock 4(12) j 2(14) k 3(13) q 6(10) q 7(9) logic symbol v cc = pin 16 gnd = pin 8 511 2 4 3 6 7 1 14 12 13 10 9 15 j q cp k q s d c d j q cp k q s d c d dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v out p ut low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v v or v v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i ih input high current j, k , clock set, clear 20 40 m a v cc = max, v in = 2.7 v i ih j, k , clock set, clear 0.1 0.2 ma v cc = max, v in = 7.0 v i il input low current j, k , clock set, clear 0.4 0.8 ma v cc = max, v in = 0.4 v i os output short circuit current (note 1) 20 100 ma v cc = max i cc power supply current 8.0 ma v cc = max note 1: not more than one output should be shorted at a time, nor for more than 1 second.
http://onsemi.com 3 ac characteristics (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit test conditions f max maximum clock frequency 25 33 mhz v 50v t plh clock clear set to out p ut 13 25 ns v cc = 5.0 v c l = 15 p f t plh t phl clock, clear, set to output 25 40 ns c l = 15 pf ac setup requirements (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit test conditions t w clock high clear, set pulse width 25 ns t data setup time e high 20 ns v =50v t s data setu time high data setup time e low 20 ns v cc = 5.0 v t h hold time 5.0 ns
http://onsemi.com 4 package dimensions n suffix plastic package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
http://onsemi.com 5 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z m suffix soeiaj package case 96601 issue o
http://onsemi.com 6 notes
http://onsemi.com 7 notes
http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong 80044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1418549 phone : 81354878345 email : r14153@onsemi.com fax response line : 3036752167 8003443810 toll free usa/canada on semiconductor website: http://onsemi.com for additional information, please contact your local sales representative. sn74ls109a/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone: (+1) 3033087140 (mf 2:30pm to 5:00pm munich time) email: onlitgerman@hibbertco.com french phone: (+1) 3033087141 (mf 2:30pm to 5:00pm toulouse time) email: onlitfrench@hibbertco.com english phone: (+1) 3033087142 (mf 1:30pm to 5:00pm uk time) email: onlit@hibbertco.com
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